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A Look at Modern CPU Fabrication
In the heady days of the first computers, vacuum tubes were the driving force behind calculations by virtue of their switching function. This was all overturned with the coming of the transistor, an invention which was officially pioneered in AT & T's Bell Labs in 1947. The transistor was a revolution because of the manufacture process and the base material, silicon, which is globally abundant and therefore cheaper to manufacture.
Silicon is a semiconductor, capable of either allowing current to pass through it or halting its progress. The properties of a solid-state silicon transistor also saw it generating less heat while being more reliable than the vacuum tube. From here, it was a short hop to the IC or Integrated Circuit which saw miniaturization technology leap forward to having thousands of transistors on a single chip, circa 1965.
Further evolution led to the advent of the microprocessor, the form factor that was the foundation for the modern Central Processing Units that currently act as the heart of computer systems globally. One of the first of these chips available was Intel's 4004 microprocessor which was released in 1971. All the while, the manufacturing process for CMOS (Complimentary Metal Oxide Semiconductor) processors has remained static in some ways while evolving wildly in others.
Early Days
Since the microprocessor was designed and first released to the public, Moore's Law has dictated that on-die transistor counts will double every eighteen months. As the size of silicon substrates have decreased and transistor count has increased, so the manufacturing process has had to evolve in certain areas. First among these is the purity of the silicon used. Integrated Circuits and microprocessors that used a substrate size larger than 10 micrometers were not incredibly concerned with the purity of the silicon.
As the manufacture process moved into the realm of the nanometre, the silicon needed to be a higher quality to prevent errors and defects in the wafers. This led to more space being devoted to clean room environments to limit imperfections in the wafers produced. (To give you an idea of what we mean by 'more': one of Intel's 45nm plants sets aside 17 000 square metres of space for their clean room.)
The Basic Fabrication Process
The full step-by-step process from raw silicon to working processor is enormously complex. The broad strokes of one such process can be outlined as involving preparation, doping, masking and etching followed by extensive testing of the wafer and later, the individual die.
Silicon is purified and refined prior to being melted into a liquid form. A quartz container is typically used for this process and other elements have been known to be added to the pure silicon to alter the semiconductor properties of the final crystal. A seed crystal is lowered into the liquid silicon and the crystalline nature of the element allows the cooling process to form a single crystal around the seed crystal. Upon completion these ingots, as they are known, are usually 200mm to 300mm in diameter for CPU manufacture. This is only one of several methods of crystal growth. An example of an alternate is the Float-zone silicon method.
The resulting ingot is inspected for imperfections and those that are defect-free move on to be ground into perfect cylinders which are then sliced into wafers. These wafers are then polished and checked for flaws and warping.
Doping is a process that usually occurs via diffusion, which inserts molecules of the doping agent between gaps in the crystal lattice structure of the wafer. Ion implantation is also used. Doping can take place during the initial crystal growth stage, once the wafer has been polished or during the masking or photolithography process. Doping alters the semiconductor properties of the silicon to suit whichever application it is being applied to, creating either a p-type (positive) or n-type (negative) semiconductor. A negative metal oxide semiconductor (NMOS) is the faster of the two, but also more expensive to implement. It functions by turning on and off the flow of electrons. By contrast, a positive metal oxide semiconductor (PMOS) functions by filling electron vacancies.
Doping materials for p-type semiconductors include boron, gallium or indium while arsenic, bismuth or phosphorous can be used to create n-type semiconductors. If doping is done at this stage in the process, a silicon dioxide layer is usually grown on the wafer. This is done by thermal means in general, with the wafer being placed in a furnace for a specific time and at a predetermined temperate with a set atmospheric makeup present in the chamber. The resulting silicon dioxide (SiO2) forms part of the end product's gate dielectric, separating the source and drain of the chip or a specific area of it. This process is one aspect of the overall process that has radically altered.
Masking is part of the photolithography process. First, the wafer is coated with photoresist, a substance that reacts to light. A mask is then used to expose certain areas of the wafer to light, altering the properties of the photoresist. This process is highly complex and nothing as simple as this explanation makes it out to be. Up to a staggering 10GB of data is required to implement each layer in the masking/photolithography process.
Etching takes place when a chemical agent is used to remove the exposed photoresist as well as the oxide layer below it, leaving the bare silicon exposed in specific places. The result is a series of ridges in the wafer that are the basis for the finished processor. The unused photoresist is also cleared from the wafer, leaving the silicon wafer with an oxide layer exposed. From here, the process consists of doping the wafer, the addition of a polysilicon (which forms the basis for the logic gates in the processor), application of photoresist and subsequent photolithography followed by etching and then ion bombardment to create n- or p-wells in the chip. These wells are specific areas that will form gates in individual transistors. This process is repeated until all of the layers are completed, a process that can require upwards of twenty layers in the sandwich.
A layer of metal will be inserted every few layers, to carry electrical connections between transistors. This entire process can take weeks for a single wafer, after which it is tested for any faults or dead areas on the wafer. A wafer that passes the tests is sliced into individual dies; these dies are then rigorously tested. Some processors will end up dead and unable to function. Others will be downgraded to a Celeron or Sempron chip after faulty areas have been circumvented by the on-die controller.
Advances
The most obvious advances made have been the transistor counts for processor dies. This number has risen from 2700 for the first commercial chip to 824 000 transistors at last count. But Moore's Law rules - Intel has demonstrated a two billion transistor chip that is currently in development.
The transistors themselves have had straining technology implemented. This occurred in 2001 and was pioneered by IBM. Straining involved either stretching the crystal lattice of silicon (in the case of NMOS transistors) or compressing it (for PMOS transistors) to speed up their respective switching speeds. A crystal lattice is the three-dimensional structure that silicon naturally binds into when forming into ingots during the initial crystal formation in the fabrication process. Silicon naturally forms into a diamond structure, as does germanium, a secondary semiconductor element.
Other advances are supposed to be in the pipeline for transistor technology in general and processor tech specifically. Speculation on this may be entertaining but won't result in anything worth committing to. The 45nm process will reduce to 32 and probably 22nm thereafter. Waiting to see what advances in wafer and transistor manipulation that will bring is the really exciting part.
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